/* D触发器 */
module D_FF(clk, reset, d_in, q_out);
	input clk, reset, d_in;
	output q_out;
	
	reg q_out;
	
	always @ (posedge reset or negedge clk)
		if(reset)
			q_out <= 1'b0;
		else
			q_out <= d_in;

endmodule